Video ULA

The video ULA is a custom Integrated Circuit (IC) developed by Acorn Computer for use in its BBC Microcomputer series. It has two functions:

• To serialise the display memory into an RGB video signal;
• To divide the 16 MHz master clock into lower frequencies for use by other ICs.

The original IC was fabricated by Ferranti as an Uncommitted Logic Array (ULA), permanently mask-programmed to Acorn's specification; part number ULA 5C094. Later, Acorn second-sourced the chip from VLSI Technologies, Inc.; this was a different design, more correctly known as the VIDPROC (Video Processor). The first revision was VC 2023, which needed a patch wire to be soldered on the motherboard; the second revision, VC 2069, was functionally and physically compatible with the video ULA. Acorn's internal part number for the VIDPROC was 201,647.

Operation

Video serialisation

On the BBC Micro, the video ULA is fitted as IC 6, slightly south-east of the centre of the board. Electronically it is attached to the DRAM data bus, which runs at 4 MHz. The bus is multiplexed so that the CPU (which is attached to the I/O bus) and the video hardware each have access at 2 MHz without risk of contention.

In MODE 7, the video ULA simply repeats the output from the SAA 5050 Teletext chip, and superimposes the cursor from the CRTC, with a matching 1 character delay.

In the ASCII modes, the display is bitmapped. The video ULA works together with the 6845 Cathode Ray Tube Controller (CRTC) to generate the RGB signal. For about one-third of each frame, the display memory is repeatedly read and ignored as the CRTC is emitting synchronisation marks and blank space. DISEN is lowered at these times. For the other two-thirds, the CRTC generates addresses in the display memory and places one on the DRAM address bus each cycle (via the address translation ICs.) The video ULA then fetches each byte from the DRAM data bus and begins converting it to an RGB signal.

Each byte fetched from the data bus is placed

in a shift register. Bits 1, 3, 5 and 7 are then used as an address to look up in a fast, 16 × 4 bit array of palette memory. The memory then outputs inverted red, green and blue values and a positive flash bit. If the flash bit, and bit 0 of the control register are both set to 1, the inverted RGB values are passed to the next stage, otherwise they are re-inverted to true RGB.

The shift register shifts left at the rate of 16 MHz (in MODEs 0 and 3), 8 MHz (MODEs 1, 4 and 6) or 4 MHz (MODEs 2 and 5.) The lowest bits are filled up with 1s, or random values on some machines. There are effectively 4 bits per pixel in every MODE; some of these may belong to the pixels following and so they are masked out by careful programming of the palette register.

The final stage includes cursor drawing, initiated by the CURSOR input and temporarily inverting the output yet again, and display blanking, forced by the CRTC via the DISEN line on pin 26 and bringing all outputs low. INVERT on pin 27, which is connected to link S26, selects between normal and reverse video, which is then produced on pins 14 (red), 12 (green) and 10 (blue).

Clock division

The 16 MHz clock line is supplied to the ULA via pin 8. The clock is divided via a chain of flip-flops into clocks of 8 MHz, 4 MHz, 2 MHz and 1 MHz, which are output on pins 7, 6, 5 and 4 respectively. These clocks are used within the ULA as well as on the motherboard, so it made sense to make them available externally. They are also of course regular, and the cycle stretching needed to interface 1 MHz devices to the I/O bus is handled elsewhere.

Interface

Control register

The video ULA control register appears in SHEILA at address &FE20. It is a write-only register but the MOS maintains a copy in RAM at address &248.

The preferred method to update the control register is via OSBYTE call 154 (&9A) with the new value in X. *FX 151,32,n should not be used as this does not update the RAM copy and the MOS will override the setting when it next toggles the flash bit.

The register is summarised as follows:

b7	b6	b5	b4	b3,	b2	b1	b0
Cursor segment 0	Cursor segment 1	Cursor segment 2	Clock rate	No. of columns		Teletext	Flash

In detail:

• Bits 7,6 and 5 control the three segments of the cursor. Once the CRTC has signalled the start of the cursor, the video ULA draws each segment in turn, if the corresponding bit is set. Segments 0 and 1 are each 1/40 or 1/80 of the display width, depending on bit 4; segment 2 is twice as wide as segment 1. This allows the cursor to match the size of the characters.
  • In the ASCII modes segment 0 coincides with the left edge of the column, and so it is always enabled.
  • In MODE 7 only segment 1 is enabled as the Teletext characters are delayed by one extra column.
  • In MODEs 0,1,2,4 and 5 the cursor perfectly overlaps the underscore character ("_").
  • In various MODEs the cursor can be made to extend into the left or right border.
• Bit 4 controls the video clock rate. The video ULA will drive the CRTC at 1 MHz (if clear) or 2 MHz (if set), causing it to fetch 40 or 80 bytes per scan line, respectively. If this bit is toggled the CRTC must be reprogrammed for the new clock rate.
• Bits 3 and 2 control the number of columns on screen:

b3	b2	Number of columns	Pixel rate
0	0	10	2 MHz
0	1	20	4 MHz
1	0	40	8 MHz
1	1	80	16 MHz

• Note:
  • If 80 columns are selected but the video clock rate is 1 MHz, the shift register will be emptied and every other text column will be 'blank', filled with logical colour 15.
  • If 10 columns are selected and the video clock rate is 2 MHz, only the odd bits of each byte will affect the display.
• Bit 1, if set, selects the Teletext input.
• Bit 0, if set, causes the colours defined as 'flashing' to be inverted. Toggling this bit regularly (as the MOS does automatically) causes the colours to blink.

The default values are as follows. These can be found in the MOS 1.20 ROM at locations &C3F7 to &C3FE:

MODE	Control register
0	&9C (%100 1 11 0 0)
1	&D8 (%110 1 10 0 0)
2	&F4 (%111 1 01 0 0)
3	&9C (%100 1 11 0 0)
4	&88 (%100 0 10 0 0)
5	&C4 (%110 0 01 0 0)
6	&88 (%100 0 10 0 0)
7	&4B (%010 0 10 1 1)

The unofficial 'extra MODEs' use the following:

MODE	Control register
8	&E0 (%111 0 00 0 0)
9	&80 (%100 0 00 0 0)
10	&84 (%100 0 01 0 0)

Palette register

The video ULA palette register appears in SHEILA at address &FE21. It is a write-only register but the MOS maintains a copy of the last value written, in RAM at address &249.

The preferred method to write to the palette register is via OSBYTE call 155 (&9B) with the value in X. The low four bits of X should contain an actual colour, as defined in the User Guide; the call will then invert bits 2, 1 and 0 before writing to RAM and to the register.

The register is summarised as follows:

b7,	b6,	b5,	b4	b3	b2	b1	b0
Address				Flash	~Blue	~Green	~Red

(~ indicates an inverted value.)

The register consists of 16 × 4-bit words of fast static RAM. A write stores bits 3 to 0 in the word addressed by bits 7 to 4. When the same word is addressed by bits 7, 5, 3 and 1 of the shift register, the given values of bits 2, 1 and 0 are inverted (under normal circumstances) and fed to the video output circuits; bit 2 enabling blue, bit 1 green, and bit 0 red. If bit 3 is set, the colour will flash when bit 0 of the control register is toggled.

For instance, calling *FX 155,211 (X=&D3, %11010011) writes &D4 (%11010100) to the register and to the RAM copy. Thereafter, when the shift register contains %1x1x0x1x, the ULA will produce non-flashing (0) yellow (011, the inverse of 100).

A total of sixteen writes are necessary to define the full palette. When a MODE has fewer than 16 colours each colour involves several words of palette memory, so that the bit pattern of the next pixel does not affect the colour of the current one. A VDU 19 statement therefore causes eight writes, four writes or one write to the palette register, depending on the MODE.

On changing to an ASCII mode, the MOS reprograms the entire palette by calling the equivalent of VDU 20, which among other things defines each logical colour in descending order. The values sent to the ULA are as follows:

MODE(s)	Palette register writes (hex)
0, 3, 4, 6	80 90 A0 B0 C0 D0 E0 F0 07 17 27 37 47 57 67 77
1, 5	A0 B0 E0 F0 84 94 C4 D4 26 36 66 76 07 17 47 57
2	F8 E9 DA CB BC AD 9E 8F 70 61 52 43 34 25 16 07

Pinout

R114 and the X line

The V₂ input receives a reference voltage of +2.2 volts, regulated by diodes D16, D17 and D18 and pulled up by the large 18 ohm resistor R114. The reference voltage also pulls up (and down) the 16 MHz clock input to pin 8, via the trace labelled X in the circuit diagram and resistor R107.

Notes

The original Ferranti part requires a heatsink. Due to a mistake in the maskwork it is effectively 'overclocked' at the standard frequency. Therefore it is sensitive to its own heat output and must be kept near ambient temperature.

During manufacture, a percentage of video ULAs were found to fail performance tests at the higher resolution modes of the Model B (MODEs 0, 1 and 2.) Rather than scrap these chips, Acorn set them aside and fitted them to the cheaper Model A, which had 16 KiB of RAM – not enough to map the entire screen in these modes. Users who upgraded their Model A to 32 KiB then sometimes discovered that the new high resolution modes would not work properly. It is not known whether they were eligible for free replacements.

Third-party hardware

In 1986, Wild Vision released Palettemate which offered 4096 colours total and up to 16 colours on screen.

In the January 1990 edition of The Micro User, Mike Cook published the schematic of Chameleon, which did not interfere with or replace the Video ULA but remapped the 8-colour RGB output of the BBC Micro to a 4096-colour palette programmed via the user port.

Rob Coleman has released an extension board, VideoNuLA, which replaces the Video ULA or VIDPROC in IC 6 and samples the A1 address line via a flying lead. As well as providing a compatible replacement for the original ICs, it also offers 12-bit colour depth, with up to 16 colours on screen from a palette of 4096 colours; pixel-by-pixel horizontal hardware scrolling; and new attribute modes which reduce resolution and use the resulting redundant bits to select a palette for each group of three, five or six pixels.

References

-- regregex 18:20, 7 October 2017 (BST)