CRTC
The 6845 CRTC (Cathode Ray Tube Controller) controls how the display is generated. It is written to with VDU 23,0 which also takes account of the current *TV and VDU 23,1 settings. The hardware is directly accessible at &FE00 and &FE01. The 6845 is used in the BBC, Master and System computers. Other display hardware is used on the Atom, Electron, and later computers
Most systems without a hardware 6845 CRTC implement setting the cursor state with registers 10 and 11 via VDU 23;10 and VDU 23;11.
Some systems extend the VDU 23,0 interface to add additional functionality. It is recommended that when this is done that register numbers &80 and higher are used.
Summary
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&FE00 - Register number
Writing to &FE00 sets the register that will be accessed through the data register. The register number is a 5-bit number 0-31, but registers 18 to 30 are reserved. Register 31 is implemented on some 6845s (but what does it do?).
Some 6845s have a status register that is read at &FE00. This returns the following information:
- bit 7: set during update, cleared by writing to Register 31.
- bit 6: set if there is a strobe input to the ~LPEN signal. It is cleared when either R16 or R17 (Light pen position) is read.
- bit 5: set during the vertical blanking period, when the VerticalCount >= VerticalDisplayed.
- other bits: usually zero, but often random
&FE01 - Register data
Using the data register reads or writes to CRTC registers. Registers are normally written to with VDU 23,0. the read/write registers have RAM copies in the VDU workspace which can be read with OSBYTE &A0.
Write-only registers return &00. Reserved registers (18 to 31) return &00.
Writing to reserved registers (does what?).
Register 0 - Horizontal total (HTC)
This 8-bit register is the number of character bytes that represents the full horizontal line, covering the displayed and non-displayed area. The displayed characters this represents is a combination of the HTC and the colour depth set with the video ULA. MODEs 0 to 3 are 128 characters wide, with HTC=127, MODEs 4 to 7 are 64 characters wide, with HTC=63.
Register 1 - Horizontal displayed (HDC)
This 8-bit register is the number of displayed character bytes per display line. As with HTC, the number of visible characters is a combination of HDC and the colour depth set with the Video ULA. MODEs 0 to 3 are 80 characters wide, MODEs 4 to 7 are 40 characters wide.
Register 2 - Horizontal sync position (HSP)
This 8-bit registers sets the position of the horizontal sync pulse measured in character bytes from the lefthand side. Increasing the HSP pushes the entire display to the left, decrementing it pushes the entire display to the right. The standard MODE 7 setting is 51, but 52 gives a more centred display.
Register 3 - Sync widths (HSW, VSW)
- bits 3-0 set the horizontal sync pulse width, with zero meaning 16
- bits 7-0 set the vertical sync pulse width, with zero meaning 16
These set the horizontal and vertical sync pulse widths, as a character byte count hortizontally and a character count vertically. These values are tied to the display standards being used, and are rarely usefully changed. In MODEs 0 to 3 the HSync width is 8, in MODEs 4 to 7 it is 4; the VSync width is always 2.
Register 4 - Vertical total (VTC)
This 7-bit register is the number of character lines that represents the full vertical screen size, covering the displayed and non-displayed area. The total number of lines usually includes a fraction part, which is set with R5
Register 5 - Vertical total adjust (VTA)
This 5-bit register sets the fractional adjustment to the total screen height, measured in pixel lines. Increasing VTA moves the screen upwards, decreasing it moves the screen downwards.
Register 6 - Vertical displayed (VDC)
This 7-bit register is the number of visible displayed character lines.
Register 7 - Vertical sync position (VSP)
This 7-bit registers sets the position of the vertical sync pulse measured in character lines from the top of the screen. When writing it with VDU 23,0 the *TV offset parameter is added to it. Increasing the VSP pushes the entire display upwards, decrementing it pushes the entire display downwards.
Register 8 - Interlace/Display delay/Cursor delay
- bit 7-6: Number of character cells to delay cursor display, 3 disables cursor
- bit 5-4: Number of character cells to delay display, 3 disables display
- bit 3-2: unused
- bit 1: 0=Sync, 1=Sync and Video
- bit 0: 0=Non-interlaced, 1=Interlaced
Register 9 - Scan lines per character (NSL)
This 5-bit register is set to the the number of scanlines displayed for each character cell, including "stripey" blank lines. It is normally set to one less than the number of scanlines, but to two less in Interlace & Sync MODEs (ie, MODE 7).
Register 10 - Cursor start line and blink type (CSL, BLK)
This 7-bit register sets the first scanline of the cursor, and its visibility and blink state.
- bit 6-5: %00=blink off, %01=no cursor, %10=slow blink, %11=fast blink
- bit 4-0: Cursor start line
The BBC VDU driver defaults to a slow blink, 1/16th of the field frequence, and switches to a fast blink, 1/32th of the field fequency, when cursors are seperated during screen editing.
A character-based VDU system that cannot program a hardware cursor can implement a character-based cursor based on the settings of Register 9 and Register 10.
- If CSL < NSL/2, use a solid block character, eg █
- If CSL >= NSL/2, use an underline character, eg _
Register 11 - Cursor end line (CEL)
This 5-bit register sets the last scanline of the cursor. If it is the same as the first cursor scanline, then the cursor is a single scanline. If it is set below the bottom of the character cell, then the cursor only extends to the bottom of the character cell.
The BBC VDU drivers actually set the cursor end line to 8 in graphics
screen MODEs, rather than the more correct 7. It is set to 9 in the
"stripey" MODEs with the start line set to 8 resulting in a cursor
of two scan lines. It is set to 19 in MODE 7 as in the hardware the
character cells are 20 scanlines high.
Register 12/13 - Screen start address
These two registers are set to the start of the display, Register 12 is the high byte and Register 13 is the low byte. This is normally a 14-bit address, but compatible hardware extends it to 16 bits.
In soft display MODEs, the character scan lines form the lower three bits of the physical address, so the address written to Registers 12/13 is the physical address divided by 8, so will be &0000-&0FFF. When the internal address counter wraps over to &1000-&1FFF it triggers the screen wrap-around.
In MODE 7 the high byte of the address is EORedd with &54 to set the written address to &2000-&2FFF. This sets MAA13 to enable the teletext display hardware, &2000-&27FF displays memory at &3C00-&3FFF, &2800-&2FFF displays memory at &7C00-&7FFF. Address lines A10-A14 are all high during teletext display, so the display address can only be adjusted within the 1024 bytes in the MODE 7 screen memory.
Register 14/15 - Cursor position
These two registers are set to the display address of the character cell holding the cursor. It is set in the same way as the screen start address in registers 12/13.
Register 16/17 - Light pen position
These two registers hold the display address of the last light pen trigger. It is a modified address in the same manner as the display start address in registers 12/13, but also has an offset from the actual triggered location that needs to be accounted for.
Writing to registers 16/17 is undefined, but extensions to the VDU 23,0 interface could allow additional functionality.
Register 18 - Cursor width
Extension to VDU 23,0. Where supported, this sets the width of the cursor in pixels. Setting it to zero sets it to the default for the selected screen MODE.
Register 18/19 - Last update address
These two registers hold the last address read to send data to the display hardware. It is a modified address in the same manner as the display start address in registers 12/13. It is only implemented on some 6845 versions.
Register 20 -
Register 31 - Register 31
MODE
Register | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
--------------+---+---+---+---+---+---+---+---+
R0 HTC |127|127|127|127|127|127|127|127|
R1 HDC | 80| 80| 80| 80| 40| 40| 40| 40|
R2 HSP | 98| 98| 98| 98| 49| 49| 49| 51|
R3 HSW b3-b0 | 8| 8| 8| 8| 4| 4| 4| 4|
VSW b7-b4 | 2| 2| 2| 2| 2| 2| 2| 2|
R4 VTC | 38| 38| 38| 30| 38| 38| 30| 30|
R5 VTA | 0| 0| 0| 2| 0| 0| 2| 2| plus *TV setting
R6 VDC | 32| 32| 32| 25| 32| 32| 25| 25|
R7 VSP | 34| 34| 34| 27| 34| 34| 27| 27|
R8 INT b1-b0 | 1| 1| 1| 1| 1| 1| 1| 1| plus *TV setting
UND b3-b2 | | | | | | | | |
DIS b5-b4 | 0| 0| 0| 0| 0| 0| 0| 1|
CUR b7-b6 | 0| 0| 0| 0| 0| 0| 0| 2|
R9 NSL | 7| 7| 7| 9| 7| 7| 9| 18|
R10 b4-b0 | 7| 7| 7| 7| 7| 7| 7| 18|
b5 | 1| 1| 1| 1| 1| 1| 1| 1| changed for editing cursor
b6 | 1| 1| 1| 1| 1| 1| 1| 1| changed by VDU 23,1
R11 | 8| 8| 8| 9| 8| 9| 9| 19|
Extensions
Extensions to the VDU 23,0 interface, or extended hardware, should probably use register numbers 128 upwards.
Known implementations
- &A0+n: Argon Light extensions
Hardware differences
There are several slightly different versions of the 6845. The BBC series require a 6845S varient as the VDU drivers depend on certain functionality:
- R3 Vertical Sync.
- R6 Vertical Displayed any odd/even value, to set to 25 in MODE 3,6,7.
- R8 Character Delay and Cursor Delay timing for MODE 7.
Jgharston 14:47, 24 December 2007 (UTC) Jgharston (talk) 22:43, 15 January 2023 (CET)
