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</td></tr></table>WikiSysophttp://beebwiki.mdfs.net/index.php?title=OSWORD_%26BE&diff=1003&oldid=prevJgharston: moved OSWORD BE to OSWORD &BE2009-07-20T12:30:00Z<p>moved <a href="/index.php?title=OSWORD_BE&action=edit&redlink=1" class="new" title="OSWORD BE (page does not exist)">OSWORD BE</a> to <a href="/OSWORD_%26BE" title="OSWORD &BE">OSWORD &BE</a></p>
<p><b>New page</b></p><div>[[Category:OSWORD]]<br />
OSBYTE &BE (190) - Disassemble code<br />
This call disassembles the supplied data to create a single line of disassembly.<br />
__TOC__<br />
<br />
==Specification==<br />
{| cellpadding="0" cellspacing="0"<br />
| || '''On entry:''' || || || '''On exit:'''<br />
|-<br />
| colspan="5" | '''Control block'''<br />
|- valign="top"<br />
| &00 || Send block length (&10) || || || <br />
|- valign="top"<br />
| &01 || Receive block length (&20) || || || <br />
|- valign="top"<br />
| &02 || CPU number || || &02 || Number of bytes disassembled<br />
|- valign="top"<br />
| &03 || Flags (&00) || || &03 || Result flags<br />
|- valign="top"<br />
| &04 || Address disassembly comes from ||&nbsp;|| &04... || CR-termined string<br />
|- valign="top"<br />
| &08... || Data to be disassembled || || || <br />
|}<br />
<br />
You send the routine the address of the disassembly, and also the bytes that<br />
are at that address for it to disassemble. Most CPUs have instructions with<br />
a maximum length of four bytes, but some have longer instructions, eg the<br />
80x86 has some instructions 6 bytes long. So, you should provide eight bytes<br />
(two words) to disassemble. This simplifies the routine so that it does not<br />
have to attempt to read the bytes directly from memory itself.<br />
<br />
In the returned control block, XY+3 contains the actual number of bytes<br />
disassembled, and so is the value by which to increase the address pointer<br />
to disassemble the next instruction.<br />
<br />
The status byte at XY+2 holds flags about the disassembly:<br />
<br />
* If b7=0, it was a valid instruction.<br />
* If b7=1, it could not be disassembled, and the returned text string is the CPU's equivalent of "EQUB &xx".<br />
<br />
* If b6=1, then the disassembled instruction terminates a piece of code, such as an unconditional return or jump. The disassembler program can use this bit to print a blank line to clarify listings.<br />
<br />
The bottom six bits are used by different disassembly routines for different purposes.<br />
<br />
In the entry control block, XY+2 holds the CPU control number:<br />
0 reserved 44 ARM<br />
2 6502 48 80486 <br />
8 8008 58 80586<br />
9 6809 65 6502/65C02/6512<br />
11 pdp11 68 68x00 series<br />
12 6512 80 Z80, Zilog mnemonics<br />
18 80186 85 8080/8085, Zilog mnemonics<br />
28 80286 86 80x86 series<br />
30 oggin 89 INS8900<br />
32 32016 94 9440 series<br />
38 80386 99 9900<br />
65186<br />
<br />
A call with XY+0 set to 8 will return a string at XY+4 holding the name of<br />
the processor the routine disassembles. This call can be used to check if a<br />
specific disassembly routine is available.<br />
<br />
Calling with XY+0 set to 8 also returns a flag in XY+3 with the following<br />
information:<br />
* b0-b1: CPU address width, 0=16, 1=24, 2=32<br />
* b2-b3: CPU data width, 0=bytes, 1=16-bit words, 2=32-bit words<br />
* b4: Disassembly base, 0=hex, 1=octal<br />
<br />
==Examples==<br />
===Disassembler===<br />
A simple disassembly program would be the following:<br />
10 REM Disassembly test program 1<br />
20 REM By J.G.Harston<br />
30 DIM ctrl% 31:X%=ctrl%:Y%=X% DIV 256<br />
40 INPUT "Address: &"A$:ADDR%=EVAL("&"+A$)<br />
50 A%=190:REPEAT<br />
60 !X%=&2010:X?2=80 :REM Z80<br />
70 X%!4=ADDR% :REM Address<br />
80 X%!8=!ADDR% :REM Data at the address<br />
90 CALL &FFF1<br />
100 PRINT;~ADDR%;" ";<br />
110 FOR Z%=ADDR% TO ADDR%+X%?3-1<br />
120 PRINT;~?Z%;" ";:NEXT<br />
130 PRINTTAB(20);$(X%+4):IF(X%?2AND64):PRINT<br />
140 ADDR%=ADDR%+X%?3<br />
150 UNTIL0<br />
<br />
===CPU Name===<br />
The following code tests to see if a specific disassembly routine exists and<br />
returns its name or a null sting if no disassembly code is available.<br />
DEFFNDis_Name(cpu%)<br />
!X%=&2008:X%?2=cpu%:X%!4=0:A%=190:CALL &FFF1<br />
IF X%!4 THEN =$(X%+4) ELSE =""<br />
<br />
==CPU Details==<br />
===6502 (cpu 2)===<br />
The 6502 disassembly routine (type number 2) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RTS, RTI or JMP<br />
* b5-0: unused, zero<br />
<br />
===6809 (cpu 9)===<br />
The 6809 disassembly routine (type number 9) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is unconditional jump<br />
* b5-0: unused, zero<br />
<br />
===PDP-11 (cpu 11)===<br />
The PDP-11 disassembly routine (type number 11) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RTS, RTI or JMP<br />
* b5-0: unused, zero<br />
<br />
===65C12 (cpu 12)===<br />
The 65C12 disassembly routine (type number 12) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RTS, RTI, JMP or BRA<br />
* b5-1: unused, zero<br />
* b0: Instruction specific to 65C12<br />
<br />
The 65C12 disassembly routine recognises the extra instructions on the<br />
65C12. <br />
<br />
===Oggin (cpu 30)===<br />
The oggin disassembly routine (type number 30) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RET or JMP<br />
* b5-1: unused, zero<br />
* b0: extended oggin instruction set<br />
<br />
For further information, see "An Introduction to the oggin machine", David<br />
Budgen, University of Stirling Computing Science Department <ref>"An<br />
Introduction to the oggin machine", David Budgen, University of Stirling<br />
Computing Science Department</ref>.<br />
<br />
===32000 (cpu 32)===<br />
The PDP-11 disassembly routine (type number 11) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RTS, RTI or JMP<br />
* b5-0: unused, zero<br />
<br />
===ARM (cpu 44)===<br />
The ARM disassembly routine (type number 44) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is unconditional jump<br />
* b5-0: unused, zero<br />
<br />
===6502 Series (cpu 65)===<br />
The generic 6502 series disassembly routine (type number 65) returns the<br />
following information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is RTS, RTI, JMP or BRA<br />
* b5-2: unused, zero<br />
* b1: instruction specific to Rockwell R65C02<br />
* b0: instruction specific to 65C12<br />
<br />
The generic 6502 series disassembly routine recognises the extra<br />
instructions on the 65C12 and the extra instructions on the Rockwell R65C02.<br />
<br />
===Z80 (cpu 80)===<br />
The Z80 disassembly routine (type number 80) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is unconditional RET, JP or JR<br />
* b5-b2: unused, zero<br />
* b1: Instruction not on the 8080/8085<br />
* b0: Undocumented instruction<br />
<br />
The Z80 disassembly routine recognises the undocumented instructions using<br />
the index registers as 8-bit register pairs, labelling them IXL, IXH, IYL<br />
and IYH, and the Shift Left and Set instructions CB30 to CB38.<br />
<br />
===8080/8085 (cpu 85)===<br />
The 8080/8085 disassembly routine (type number 85) returns the following<br />
information in the status byte:<br />
* b7: could not be disassembled<br />
* b6: instruction is unconditional RET or JP<br />
* b5-b0: unused, zero<br />
<br />
==References==<br />
<references /><br />
<br />
[[User:Jgharston|Jgharston]] 15:20, 25 May 2009 (UTC)</div>Jgharston