Having to be carried out in real time for every bus cycle, the address translation must be done in hardware. Although the task was a potential candidate for a ULA, Acorn chose to implement it in SSI logic. Either way it would have significantly added to the cost of the BBC Micro. Such translation is justified because:
- the CPU, video ULA and Teletext chip need for memory to be presented in different ways;
- for speed the display must be scrolled in hardware, which means a virtual address space must be created to 'wrap around' the display memory area;
- the display memory area, which varies in size, must be moved to the end of RAM. This is because:
On the Electron, address translation becomes part and parcel of the ULA's video display activities. This cut-down machine does away with hardware scrolling and Teletext, but the display memory layout is identical to the BBC Micro's MODEs 0 to 6.
The Model B+ expands the subsystem to map 32K of shadow RAM into the address space. The display memory can optionally be moved to shadow RAM, making it visible only to the CRTC and the VDU routines in the MOS, and allowing user memory to extend to the end of main RAM. (For compatibility with games and other programs that update display memory directly, this shadow display can be turned off.)
From the profits of the BBC Micro, Acorn were able to commission several new ULAs for the Master series, one of which implements an advanced memory management service backward-compatible with the Model B and B+.
DRAM address space
The DRAM address bus is a 7 bit bus of lines connecting the address translation buffers to the DRAM memory banks. It is a diplexed bus that runs at 8 MHz, transmitting two addresses for each data transfer at 4 MHz.
The first seven bits transmitted form the row address (ROW); the CRTC visits all rows several times a millisecond and refreshes the DRAM array automatically. The last seven bits form the column address (COL).
These fourteen bits, together with a signal line from IC 28 pin 6 to the north pin of S25, form a 15 bit address space. The bits of the address space are interpreted as follows:
|Bank select||Column address||Row address|
On the Model A, there is only one DRAM bank as standard so DA14 is unused.
The read/~write line
The read/~write line, supplying the DRAM array, is gated by the buffer ICs parallel to the DRAM address bus. It is only lowered in CPU mode, when the column address is transmitted, and the CPU is writing to RAM (R/~W and A15 both low.) When the CPU is writing to the video ULA registers, the DRAM arrays are disabled but the R/~W line is also held high to prevent spurious writes.
Address translation modes
There are three address translation modes. The BBC micro rapidly alternates between CPU and one of the others, depending on the screen MODE. While reprogramming the CRTC to set the screen MODE, the MOS sets one of its address outputs (MA13) high or low to select the translation mode.
The translation hardware does use two outputs of the addressable latch IC 32, attached to the system VIA, but only in HI RES mode to set the size of the display memory area.
When the 2 MHz monotonic clock is low, the CPU has control of the DRAM data bus. No translation is carried out, thus A0..A14 maps directly to DA0..DA14 of the DRAM address space. This mode does not guarantee to refresh the DRAM.
CPU ROW is gated by IC 12 and CPU COL by IC 13.
This mode is selected when the 2 MHz clock, and the CRTC's MA13 output (TTX VDU) are high. This mode delivers data to the SAA 5050 Teletext generator to display MODE 7. The CRTC's row address (RA) lines are ignored as the SAA 5050 contains its own scanline counter, and expects the same 40 bytes to be presented on each scanline of the text row. Thus:
|AA3||all 1||MA9..7||MA6 ^ ~1MHz||MA5..MA0|
In MODE 7 the MOS ensures that MA11 is set and MA12 clear, so that AA3 is 1. This arrangement automatically provides hardware scrolling as MA10, raised on overflow, is ignored and all addresses are in the range &7C00 to &7FFF. By toggling AA3 an application can instantly switch to a second screen at &3C00 to &3FFF.
The MA6 line is XORed with the 1 MHz monotonic clock, so two distinct bytes are fetched in TTX VDU mode every microsecond. The buffer IC 15 delivers one to the SAA 5050 and discards the other. Therefore all 128 DRAM rows are refreshed every scanline, meaning the longest any row goes without a refresh is 88 μs. Without toggling MA6 it would be 1.96 ms.
TTX ROW is gated by IC 10 and TTX COL by IC 11.
This mode is selected when the 2 MHz clock is high and MA13 (TTX VDU) is low. This mode delivers data to the video ULA to display MODEs 0 to 6. The mapping of row and memory address lines to the DRAM address space was designed for efficient printing of text. Normally a character can be displayed by writing 8, 16 or 32 consecutive bytes. Thus:
where AA3..AA0, the adjusted address, is MA11..MA8 with corrections to stay within the display memory area.
The maximum time between refreshes of any row of DRAM is 480 μs in MODEs 0..2, 488 μs in MODEs 4..5, 608 μs in MODE 3, and 616 μs in MODE 6. (In MODEs 3 and 6, RA3 going high forces DISEN low and so the bottom two scanlines of each text row are black. Character rows 0 and 1 are refreshed during these scanlines.)
HI RES ROW is gated by IC 8 and HI RES COL by IC 9.
Calculation of the adjusted address
When MA12 goes high this corresponds to the current display address overrunning the end of RAM at &8000. In order to implement hardware scrolling the address must be 'wrapped around' to restart from the beginning of display memory. In the bitmapped MODEs this is done in hardware in several stages:
- State: the addressable latch IC 32 is programmed with the encoded display size;
- Decode: in case of overflow, four logic gates decode the state into a one's-complemented number of 2K units;
- Subtract: a quad adder IC 39 subtracts this number from the relevant address lines;
- Diplex: the result is fed to an address translation buffer IC 9 and diplexed onto the address bus as normal.
Outputs 4 and 5 of the addressable latch, labelled C0 and C1, select the size of the display memory. From these the decoder generates outputs, to be fed into the B side of the quad adder, as follows:-
|MA12||C1||C0||B4||B3||B2||B1||Amount to subtract||Restart address||MODEs|
-- beardo 16:38, 20 March 2007 (UTC)
MA is the character address generated by the 6845, and RA is the line number within the current character row.
The top bit (value 0x2000) of MA controls whether an address is decoded as a teletext or high resolution address. (Note that this is independent of the teletext select bit in the video ULA.)
The generated address MA will be between 0x600 and (roughly) 0x19FE. Note that this never has the 0x2000 top bit set. Then:
Unwrapped real memory address = (MA << 3) | (RA & 7)
This explains why the screen start address must be divided by 8 before programming the 6845. RA is in the range 0-7 except in the gaps between rows in MODES 3 and 6. The display is blanked in these gaps. If the unwrapped address exceeds 0x7FFF it is adjusted as described above.
The 6845 is programmed with a start address between 0x2000 and 0x23FF to display data from 0x3C00 to 0x3FFF or with a start address between 0x2800 and 0x2BFF to display data from 0x7C00 to 0x7FFF. These address always have the top bit set.
Real memory address = (MA & 0x800) << 3 | 0x3C00 | (MA & 0x3FF)
This handles wrapping at 1K by ignoring the 0x400 bit. The scan line number RA is ignored so the same memory addresses are repeated for every scan line in a character row.
If the 6845 is programmed with a start address of 0x2400 it accesses memory from 0x3C00 to 0x3FFF then 0x7C00 to 0x7FFF giving a 2K linear buffer.