Difference between revisions of "DRAM chips"
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==Model A/B== | ==Model A/B== | ||
| − | The Model B uses a total of sixteen 4816 DRAM chips to give it 32K of RAM. These chips are arranged in two banks of eight chips, /CAS0 and /CAS1. Each chip provides one bit of storage for 16,536 (16K) memory locations. The Model A uses only one bank, /CAS1. The use of either or both memory banks is controlled by selection jumper S25. | + | The Model B uses a total of sixteen 4816-type DRAM chips to give it 32K of RAM. These chips are arranged in two banks of eight chips, /CAS0 and /CAS1. Each chip provides one bit of storage for 16,536 (16K) memory locations. The Model A uses only one bank, /CAS1. The use of either or both memory banks is controlled by selection jumper S25. |
Errors in a particular bit will correspond to a specific IC: | Errors in a particular bit will correspond to a specific IC: | ||
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| IC53 || IC54 || IC55 || IC56 || IC57 || IC58 || IC59 || IC60 | | IC53 || IC54 || IC55 || IC56 || IC57 || IC58 || IC59 || IC60 | ||
|} | |} | ||
| + | |||
| + | Models produced for export to Germany and the USA use a different board layout, and the ICs are numbered differently. | ||
| + | |||
| + | ==Model B+== | ||
| + | The Model B+ uses eight 4164-type DRAM chips to provide 64K of RAM. (32k of general RAM, 20K of shadow screen RAM, and 12K of sideways RAM.) The eight chips are arranged in one single bank, with each chip providing one bit for all 64K memory locations. | ||
| + | |||
| + | Because the B+ only has one bank of memory, it is not possible to selectively disable RAM chips to help diagnose a fault. Errors with a particular bit will still correspond to a specific IC: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |+ Model B+ | ||
| + | |- style="text-align:center;vertical-align:top" | ||
| + | ! D0 !! D1 !! D2 !! D3 !! D4 !! D5 !! D6 !! D7 | ||
| + | |- | ||
| + | | IC55 || IC56 || IC57 || IC58 || IC59 || IC60 || IC61 || IC62 | ||
| + | |} | ||
| + | |||
| + | ===Model B+ 128K=== | ||
| + | The 128K variant of the B+ has a daughter-board fitted, which provides a further 64K of RAM. This additional RAM is used solely as four banks of sideways RAM. It is populated with two 4464-type DRAM chips, each of which provide four bits for all 64K memory locations. The bits are provided by the DRAM chips in a non-sequential order, this makes the daughter-board design simpler, and has no material effect of the machine's operation: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |+ Model B+ Daughterboard | ||
| + | |- style="text-align:center;vertical-align:top" | ||
| + | ! D0 !! D1 !! D2 !! D3 !! D4 !! D5 !! D6 !! D7 | ||
| + | |- | ||
| + | | IC4 || IC4 || IC4 || IC3 || IC4 || IC3 || IC3 || IC3 | ||
| + | |} | ||
| + | |||
| + | The B+ circuit diagram indicates that the location where the daughter-board is fitted (IC96) was intended as an optional replacement for the eight 4164-type DRAM chips fitted to the board (i.e. using two 4464-type chips instead). It is not known if any machines were shipped with RAM on a daughter-board only. | ||
[[Category:Hardware]][[Category:Repair]] | [[Category:Hardware]][[Category:Repair]] | ||
Revision as of 06:46, 22 February 2020
Model A/B
The Model B uses a total of sixteen 4816-type DRAM chips to give it 32K of RAM. These chips are arranged in two banks of eight chips, /CAS0 and /CAS1. Each chip provides one bit of storage for 16,536 (16K) memory locations. The Model A uses only one bank, /CAS1. The use of either or both memory banks is controlled by selection jumper S25.
Errors in a particular bit will correspond to a specific IC:
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | |
|---|---|---|---|---|---|---|---|---|
| /CAS0 | IC61 | IC62 | IC63 | IC64 | IC65 | IC66 | IC67 | IC68 |
| /CAS1 | IC53 | IC54 | IC55 | IC56 | IC57 | IC58 | IC59 | IC60 |
Models produced for export to Germany and the USA use a different board layout, and the ICs are numbered differently.
Model B+
The Model B+ uses eight 4164-type DRAM chips to provide 64K of RAM. (32k of general RAM, 20K of shadow screen RAM, and 12K of sideways RAM.) The eight chips are arranged in one single bank, with each chip providing one bit for all 64K memory locations.
Because the B+ only has one bank of memory, it is not possible to selectively disable RAM chips to help diagnose a fault. Errors with a particular bit will still correspond to a specific IC:
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 |
|---|---|---|---|---|---|---|---|
| IC55 | IC56 | IC57 | IC58 | IC59 | IC60 | IC61 | IC62 |
Model B+ 128K
The 128K variant of the B+ has a daughter-board fitted, which provides a further 64K of RAM. This additional RAM is used solely as four banks of sideways RAM. It is populated with two 4464-type DRAM chips, each of which provide four bits for all 64K memory locations. The bits are provided by the DRAM chips in a non-sequential order, this makes the daughter-board design simpler, and has no material effect of the machine's operation:
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 |
|---|---|---|---|---|---|---|---|
| IC4 | IC4 | IC4 | IC3 | IC4 | IC3 | IC3 | IC3 |
The B+ circuit diagram indicates that the location where the daughter-board is fitted (IC96) was intended as an optional replacement for the eight 4164-type DRAM chips fitted to the board (i.e. using two 4464-type chips instead). It is not known if any machines were shipped with RAM on a daughter-board only.
