Difference between revisions of "DRAM chips"
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|+ Model A/B | |+ Model A/B | ||
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| − | ! | + | !!! D0 !! D1 !! D2 !! D3 !! D4 !! D5 !! D6 !! D7 |
| + | |- | ||
| + | ! /CAS0 | ||
| + | | IC61 || IC62 || IC63 || IC64 || IC65 || IC66 || IC67 || IC68 | ||
|- style="text-align:center;vertical-align:top" | |- style="text-align:center;vertical-align:top" | ||
| − | ! | + | ! /CAS1 |
| − | | | + | | IC53 || IC54 || IC55 || IC56 || IC57 || IC58 || IC59 || IC60 |
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[[Category:Hardware]][[Category:Repair]] | [[Category:Hardware]][[Category:Repair]] | ||
Revision as of 06:17, 22 February 2020
Model A/B
The Model B uses a total of sixteen 4816 DRAM chips to give it 32K of RAM. These chips are arranged in two banks of eight chips, /CAS0 and /CAS1. Each chip provides one bit of storage for 16,536 (16K) memory locations. The Model A uses only one bank, /CAS1. The use of either or both memory banks is controlled by selection jumper S25.
Errors in a particular bit will correspond to a specific IC:
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | |
|---|---|---|---|---|---|---|---|---|
| /CAS0 | IC61 | IC62 | IC63 | IC64 | IC65 | IC66 | IC67 | IC68 |
| /CAS1 | IC53 | IC54 | IC55 | IC56 | IC57 | IC58 | IC59 | IC60 |
