Difference between revisions of "6502"
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[[Category:Programming]] | [[Category:Programming]] | ||
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Programming information on 6502 series machine code. | Programming information on 6502 series machine code. | ||
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== Overview == | == Overview == | ||
| − | The 6502 is an 8 bit processor with a 16 bit address bus, giving a memory addressing range of 65536 bytes. | + | The 6502 is an 8 bit processor with a 16 bit address bus, giving a memory |
| − | The 6502 has no direct input/output capabilities and hence hardware must be memory mapped.<br /> | + | addressing range of 65536 bytes. It has one general purpose register, two |
| + | indexing registers, a stack register, a status register and program | ||
| + | counter.<br /> | ||
| + | The 6502 has no direct input/output capabilities and hence hardware must be | ||
| + | memory mapped.<br /> | ||
All addresses are comprised of two bytes and are arranged little endian.<br /> | All addresses are comprised of two bytes and are arranged little endian.<br /> | ||
| − | There are three interrupt types including non-maskable, maskable and software. | + | There are three interrupt types including non-maskable, maskable and |
| + | software. An interrupt bit in the status register controls maskable | ||
| + | interrupts. On receipt of an interrupt the processor will push the registers | ||
| + | on the stack and vector through the following addresses: | ||
* FFFAH/FFFBH Non Maskable Interrupt (NMI) | * FFFAH/FFFBH Non Maskable Interrupt (NMI) | ||
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== Instruction Set == | == Instruction Set == | ||
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The 6502 supports 56 instruction types in the following categories: | The 6502 supports 56 instruction types in the following categories: | ||
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=== Register Move/Increment/Decrement === | === Register Move/Increment/Decrement === | ||
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LDA<br /> | LDA<br /> | ||
LDX<br /> | LDX<br /> | ||
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=== Jumps/Branches === | === Jumps/Branches === | ||
| − | |||
JMP<br /> | JMP<br /> | ||
BRK<br /> | BRK<br /> | ||
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=== Stack === | === Stack === | ||
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PHP<br /> | PHP<br /> | ||
PLP<br /> | PLP<br /> | ||
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Examples are in pseudo assembly language, with labels where appropriate. | Examples are in pseudo assembly language, with labels where appropriate. | ||
| − | === Multi | + | === Multi-byte Addition === |
CLC<br /> | CLC<br /> | ||
LDA a_lo_byte<br /> | LDA a_lo_byte<br /> | ||
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=== Block Move === | === Block Move === | ||
| − | The two addresses are stored in zero page. | + | The two addresses are stored in zero page. The Y register contains the size |
| + | of the block to move minus one. | ||
.next_byte<br /> | .next_byte<br /> | ||
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== Internet resources == | == Internet resources == | ||
| − | + | Because of its enduring popularity as the core of the Commodore 64 and as an | |
| − | Because of its enduring popularity as the core of the Commodore 64 and as an embedded systems controller, there are a number of Web sites and pages about the 6502 architecture. | + | embedded systems controller, there are a number of Web sites and pages about |
| + | the 6502 architecture. Here are just a couple of them: | ||
* ''[http://www.6502.org/ 6502.org]'' has documents, code resources and a forum about the microprocessor. | * ''[http://www.6502.org/ 6502.org]'' has documents, code resources and a forum about the microprocessor. | ||
* ''[http://www.nvg.org/bbc/doc/6502.txt A detailed analysis]'' (C64 oriented) of instruction timings and undocumented opcodes. | * ''[http://www.nvg.org/bbc/doc/6502.txt A detailed analysis]'' (C64 oriented) of instruction timings and undocumented opcodes. | ||
Latest revision as of 16:47, 12 November 2017
Programming information on 6502 series machine code.
Contents
Overview
The 6502 is an 8 bit processor with a 16 bit address bus, giving a memory
addressing range of 65536 bytes. It has one general purpose register, two
indexing registers, a stack register, a status register and program
counter.
The 6502 has no direct input/output capabilities and hence hardware must be
memory mapped.
All addresses are comprised of two bytes and are arranged little endian.
There are three interrupt types including non-maskable, maskable and
software. An interrupt bit in the status register controls maskable
interrupts. On receipt of an interrupt the processor will push the registers
on the stack and vector through the following addresses:
- FFFAH/FFFBH Non Maskable Interrupt (NMI)
- FFFCH/FFFDH Processor Reset
- FFFEH/FFFFH Maskable Interrupt
- FFFEH/FFFFH Software Interrupt (Break)
Instruction Set
The 6502 supports 56 instruction types in the following categories:
Arithmetic/Logical
ADC
SBC
AND
ASL
LSR
ROL
ROR
CMP
CPX
CPY
DEC
EOR
ORA
BIT
Register Move/Increment/Decrement
LDA
LDX
LDY
STA
STX
STY
TAX
TSX
TXA
TXS
DEC
DEX
DEY
INC
INX
INY
Jumps/Branches
JMP
BRK
JSR
RTI
RTS
BCC
BCS
BEQ
BMI
BNE
BPL
BVC
BVS
Stack
PHP
PLP
PHA
PLA
Flags
CLC
SEC
CLI
SEI
CLV
CLD
SED
Other
NOP
Memory Addressing
The 6502 has the following addressing modes:
Implied
Immediate
Zero Page
Absolute
Zero Page Indexed
Absolute Indexed
Zero Page Pre Indirect
Zero Page Post Indirect
Miscellanous Routines
Some simple tasks are very common in 6502 programming.
Examples are in pseudo assembly language, with labels where appropriate.
Multi-byte Addition
CLC
LDA a_lo_byte
ADC b_lo_byte
STA c_lo_byte
LDA a_hi_byte
ADC b_hi_byte
STA c_hi_byte
Two Byte Multiplication
LDA #0
STA lo_result
STA hi_result
LDX #9
CLC
.next_bit
ROR hi_result
ROR lo_result
DEX
BEQ exit
LSR operand_1
BCC next_bit
CLC
LDA hi_result
ADC operand_2
STA hi_result
JMP next_bit
.exit
Block Move
The two addresses are stored in zero page. The Y register contains the size of the block to move minus one.
.next_byte
LDA (address_from),Y
STA (address_to),Y
DEY
BNE next_byte
Internet resources
Because of its enduring popularity as the core of the Commodore 64 and as an embedded systems controller, there are a number of Web sites and pages about the 6502 architecture. Here are just a couple of them:
- 6502.org has documents, code resources and a forum about the microprocessor.
- A detailed analysis (C64 oriented) of instruction timings and undocumented opcodes.
