Difference between revisions of "Paging in video memory"

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  RTS
 
  RTS
  
== See also ==
+
==See also==
 
* [[OSBYTE &6C]] - Select Master/Integra-B shadow memory
 
* [[OSBYTE &6C]] - Select Master/Integra-B shadow memory
* [[OSBYTE &6F]] - Select BBC B shadow memory
+
* [[OSBYTE &6F]] - Select Aries/Watford shadow memory
 
* [[OSBYTE &84]] - Read top of user memory
 
* [[OSBYTE &84]] - Read top of user memory
 
* [[Paging in video memory]]
 
* [[Paging in video memory]]
 
* [[Extended addressing]]
 
* [[Extended addressing]]
 
* http://mdfs.net/Docs/Comp/BBC/Osbyte00
 
* http://mdfs.net/Docs/Comp/BBC/Osbyte00
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----
  
 
== References ==
 
== References ==

Latest revision as of 19:26, 22 January 2021

The BBC Master, the Aries-B20 and B-32, the Integra-B and the Watford 32 RAM card have shadow screen memory. The following code (taken from HADFS[1] and HostFS[2]) will page in or out the video memory transparently using the appropriate OSBYTE call to do so.

 \ Screen selection routines
 \ =========================
 \ On entry, A=0 - select main memory
 \           A=1 - select video memory
 \ On exit,  all registers corrupted
 \
 .vramSelect
 PHA:TAX                   :\ A=0 main RAM, A=1 video RAM
 LDA #108:JSR OSBYTE       :\ Attempt to select Master/Integra-B video RAM
 PLA:INX:BNE vramOk        :\ X<>255, successful
 EOR #1:TAX                :\ A=1 main RAM, A=0 video RAM
 LDA #111:JMP OSBYTE       :\ Attempt to select Aries/Watford video RAM
 .vramOk
 RTS

Using this code, filing system or other code can selectively access main or video memory according to the standard &FFFFxxxx, &FFFExxxx and &FFFDxxxx address ranges.

 \ Decide what local memory to transfer data to/from
 \ -------------------------------------------------
 \ On entry, DADDR+0...DADDR+3=data transfer address
 \                           A=&Fx - read (load) data
 \                           A=&Ex - write (save) data
 \
 LDX &27A:BPL TransIO      :\ No Tube
 LDX DADDR+3               :\ Check transfer address &XX------
 INX:BNE TransTube         :\ Tube present, ADDR<&FFxxxxxx
 .TransIO
 AND #&F0:PHA              :\ Push transfer flag, b7=1 for IO transfer
 LDX DADDR+2               :\ Get address &--XX----
 INX:BEQ TransIOGo         :\ &FFFFxxxx - current IO memory
 INX:BEQ TransIODisplay    :\ &FFFExxxx - use current display memory
 INX:BEQ TransIOShadow     :\ &FFFDxxxx - shadow memory
 BNE TransIOGo             :\ Not &FFFDxxxx - use current IO memory
 :
 .TransIODisplay
 LDA #&84:JSR OSBYTE
 TYA:BPL TransIOGo         :\ Not shadow screen displayed
 .TransIOShadow
 LDA #1:JSR vramSelect     :\ Page in shadow memory
 PLA:ORA #1:PHA            :\ Set b0 for screen, page in video RAM
 :
 .TransIOGo
 \ At this point, the byte on the stack holds
 \   &E0 - load is to current memory
 \   &E1 - load is to screen memory
 \   &F0 - save is from current memory
 \   &F1 - save is from screen memory
 \ ie b7=1 - IO memory, b4=save/load, b0=main/video memory
 \
 \
 \ Do IO memory transfer here
 \
 \
 .TransExitDone
 PLA:BPL TransExitRelease  :\ Pop transfer flag, b7=0 - Tube release
 ROR A:BCS TransExitScreen :\ b0=1, Screen release
 RTS
 .TransExitRelease
 JMP TubeRelease           :\ Release Tube, return
 .TransExitScreen
 LDA #0:JMP vramSelect     :\ Page in main memory, return
 \
 .TransTube
 CLC:ADC #&10:ROL A        :\ Cy=1/0 for load/save
 LDA #0:ADC #0:PHA         :\ A=1/0 for load/save
 JSR TubeAction            :\ Claim Tube and start transfer
 \ At this point, the byte on the stack holds
 \   &1 - load is to Tube
 \   &0 - save is from Tube
 \ ie b7=0 - Tube memory
 \
 \
 \ Do Tube transfer here
 \
 \
 JMP TransExitDone         :\ Jump to release Tube

Electron

This is untested at present, but this appears to be the equivalent code for the Electron

\ Electron screen selection routine
\ =================================
\ On entry, A=0 - select main memory
\           A=1 - select video memory
\ On exit,  A corrupted, X,Y preserved
\
 .vramSelect
ROR A                      :\ Move selection in bit 0 to Carry
LDA &027F:BPL vramOk       :\ No shadow RAM present
ROR A:STA &FC7F            :\ Move Carry A to bit 7, set paging flag
.vramOk
RTS

See also


References

Jgharston 22:25, 25 December 2011 (UTC) Jgharston (talk) 20:38, 3 April 2015 (UTC)