Cycle stretching is a widely practiced technique which allows slower devices to be attached to the bus while allowing faster devices to operate at full speed. In the 68xx and 65xx architectures, which have no wait states, the CPU clock itself is slowed down to wait for the slow device to respond.
- the 6845 CRTC;
- the 6850 ACIA;
- the Serial ULA control register;
- STATID, the Econet station number at &FE18;
- the two 6522 VIAs;
- the 7002 ADC;
- and of course, the 1 MHz bus (FRED and JIM).
- The ROM in IC 100 is read at 2 MHz by default, but can be read at 1 MHz by setting link S18 south.
(Some other devices, such as the keyboard, 76489 PSG and 5220 speech synthesiser, are too slow to hold up the I/O bus or to deserve memory mapped addresses, and are reachable on the slow bus through the system VIA.)
When the CPU accesses one of the 1 MHz addresses, IC 23 raises pin 8 which connects to IC 33 pin 1. This modifies the 6502's ΦIN input, extending the current cycle to twice or three times its normal length. The ambiguity occurs because the cycle may have started in or out of sync with the 1 MHz clock. Once the CPU has been synchronised, the length of each cycle can be predicted by machine code analysis.
Cycle stretching has a significant impact on all time-critical machine code, especially interrupt service routines and code polling the VIA timers. Such code must be carefully designed so that the reduction in speed does not cause it to overrun the available time. Equally, when the code is to be run in an emulator, the latter must take care to reproduce the timings faithfully.
For further details on the timing of the 1 MHz bus (which applies equally to the other 1 MHz devices), please see p.443 of the Advanced User Guide.
-- beardo 18:24, 1 November 2006 (GMT)